1. Field of the Invention
The present invention relates to a system for and method of supporting the logic design of an LSI (large-scale integrated circuit) and the like, and more specifically, to a logic design support system and method capable of appropriately performing logic verification even in a case that a “generate” statement is used when the design is generated using Verilog and the like as a hardware description language (HDL).
2. Description of the Related Art
Generally, in designing and fabricating a semiconductor device such as an LSI, hardware is described in a hardware description language, logic verification is performed by logic synthesis based on the description, and then the semiconductor device is practically fabricated. As an LSI to be designed becomes larger, the amount of descriptions to be presented by a designer increases. To reduce the work of the designer by decreasing the amount of descriptions in describing the hardware, it is effective to efficiently describe the structure which is repeatedly presented in the hardware description. When a designing process is performed in the HDL, a configuration of a hierarchy of n layers per type or a generate statement can be effectively utilized to simplify the description of a repetitive structure, n being an integer larger than one. With the Verilog which is frequently used as an HDL, the generate statement can be used, and the amount of descriptions at an RTL (register transfer level) can be reduced using the generate statement.
However, a frequently repeated description makes it difficult for an automatic verification tool to automatically match a register from a tree structure of a net list when logic verification is performed, and the logic verification requires a longer time. The reason for the problem is that a general-purpose logic verification tool performs a verification on each logic cone segmented by a register for matching between a verifying RTL and an RTL to be verified while there are a number of the same tree structures of a net list under the hierarchy of n layers per type, thereby disabling the verification tool to automatically perform matching. When a generate statement is used, a logic synthesis tool arbitrarily generates a hierarchical instance name in the generate statement. At this time, in a black box under the hierarchy in which an instance name is automatically generated, since the correspondence of input/output pins cannot be specified, a point to be verified cannot be verified. Practically, when a hierarchy that cannot be logically verified such as a hard macro is to be verified in a black box, the input/output pin of the black box functions as a start point and an end point of the verification. Therefore, the logic verification cannot be correctly performed unless the position of the input/output pin is appropriately set by the designer.
The Japanese Patent Laid-Open Application No. 2000-11010 (JP-A-2000-011010) discloses a logic synthesis method in a logic design support system for extracting the type and number of cells being used, an instance name, and a node name from a schematic circuit diagram in a circuit changing operation for changing specifications and the like and performing again the logic synthesis using the extracted instance and the like.
The Japanese Patent Laid-Open Application No. 2003-85221 (JP-A-2003-085221) discloses an automated hierarchical RTL system for easily matching an RTL description and a synthesized logic circuit by converting each logic description of an RTL module into a hierarchical instance to be stored as input/output signal information about the description, and structuring a hierarchy of RTL modules using the hierarchical instances of the modules.
The Japanese Patent Laid-Open Application No. 2006-260288 (JP-A-2006-260288) discloses a method of reading information about a logic circuit having a hierarchy structure, and moving an instance belonging to a predetermined hierarchy to another hierarchy. In this method, when an instance is moved to another hierarchy, a hierarchy port newly required for the movement is generated and connected, and an unnecessary hierarchy port is disconnected and removed with the signal for the instance connected, thereby easily performing an operation of reconfiguring the logic circuit.
The Japanese Patent Laid-Open Application No. 2006-285333 (JP-A-2006-285333) discloses a behavioral synthesis apparatus capable of improving design efficiency by converting supplementary information to be added to a behavioral level circuit description into supplementary information to be added to an RTL circuit description. The apparatus includes: behavioral synthesis means for generating an RTL circuit description based on a behavioral level circuit description, and generating information about the correspondence between the behavioral level circuit description and the RTL circuit description based on the difference between them; and supplementary information conversion means for converting the supplementary information added to the behavioral level circuit description into the supplementary information to be added to the RTL description based on a predetermined conversion rule and the information about the correspondence generated by the behavioral synthesis means.
As described above, in the logic design support system using Verilog as an HDL, when a hierarchy description is made in a generate statement in the input RTL, there arises the problem that it is hard to verify a register under the hierarchy, or a hierarchy to be verified as a black box cannot be verified.